This invention relates generally to integrated circuits and, more specifically, to anti-fuse structures in integrated circuits.
Programmable integrated circuits include such devices as field-programmable gate arrays and programmable read-only memories (PROMS). Such devices may include elements such as fuses or anti-fuses to enable them to be programmed.
Field programmable gate arrays include a large number of logic elements, such as AND gates and OR gates, which can be selectively coupled together by devices like fuses or anti-fuses to perform user-designed functions. The several types of PROMS, including standard, write-once PROMS, erasable programmable read-only memories (EPROMS), electrically erasable programmable read-only memories (EEPROMS), etc., usually comprise an array of memory cells arranged in rows and columns which can be programmed to store user data. An unprogrammed anti-fuse gate array or PROM is programmed by causing selected anti-fuses to become conductive.
Anti-fuses include a material which initially has a high resistance but which can be converted into a low resistance material by the application of a programming voltage. For example, amorphous silicon (A-Si), which has an intrinsic resistivity of approximately 1 megohm-cm, can be fashioned into 1 micron wide vias having a resistance of approximately 1-2 gigohms. These vias can then be transformed into a low resistance state by the application of a voltage in the range of 10-12 volts d.c. to form vias having a resistance less than 200 ohms. These low resistance vias can couple together logic elements of a field programmable gate array so that the gate array will perform user-defined functions or connect large functional blocks, or can serve as memory cells of a PROM.
An anti-fuse device is typically formed on a semiconductor wafer by depositing a bottom electrode layer, such as titanium-tungsten (TiW), depositing an oxide layer over the electrode layer, forming a via through the oxide layer to the electrode layer, and depositing A-Si into the via. A second layer of TiW can be deposited over the A-Si with an aluminum (Al) layer deposited over the TiW layer.
Problems arise in the above-described structure by "cusping" or thinning of the A-Si at the corners of the via that can lead to leakage and programming problems. Further, cusps formed in the A-Si layer can lead to poor step coverage of the TiW layer over the A-Si. This can cause an inadequate TiW barrier to be formed separating the top Al layer from the A-Si, which can compromise the reliability of the anti-fuse, because A to degrade or "poison" an anti-fuse structure by diffusing into the A-Si layer.
A prior art solution to this problem provides oxide spacers over the cusps of the A-Si. Such a structure is described in U.S. Pat. No. 5,120,679 issued to Boardman et al., the disclosure of which is incorporated herein by reference. This spacer better protects the corners of the via where the cusping or thinning of the A-Si is problematic. The spacer also improves the topography for the subsequent TiW barrier layer deposition. The use of dielectric spacers reduces leakage current and enhances reliability. However, the use of spacers may increase production time and cost. Further, the use of spacers results in reduced scalability of the structure below 1.0 micron (.mu.m).
Alternatively, another anti-fuse structure is used for technology scaled to 0.8 .mu.m, as the cross-sectional view of the anti-fuse structure in FIG. 1 illustrates. Overlying a silicon wafer substrate 8 on which a base oxide layer 9 has been formed are a first metal layer 10 (typically Al) and an inter-metal oxide (IMO) layer 12. A layer 14 of TiW is deposited and patterned to form a conductive "strap". Following formation of layer 14, a layer of A-Si 16 is deposited and then patterned to remain only in the desired locations overlying the TiW patterned layer 14. Thus, the A-Si is not deposited in the via as in the prior anti-fuse structures, but rather, forms a separate, planar layer. An oxide layer 18 is then deposited, followed by the etching of a via 20 through the oxide layer 18 to the A-Si layer 16. A barrier layer 22 of TiW is then preferably deposited over the oxide and into the via 20 to contact the A-Si layer 16. Subsequently, metal layer 24, preferably Al, is then deposited over the TiW layer, which prevents the Al layer 24 from poisoning the A-Si layer 16.
While the above-described structure is usable with 0.8 .mu.m anti-fuse technology, the integrity of the anti-fuse is dependent on the integrity of the TiW barrier layer 22. This barrier layer has a problem of cusping or thinning at the corners 21 of the via 20. This cusping makes the corners more permeable to the migration of Al atoms from layer 24, which can lead to Al layer 24 diffusing into the A-Si layer 16, thereby "poisoning" the A-Si layer 16 at that point. By "poisoning" it is meant that the conductive aluminum atoms in the A-Si layer change the conductivity of the layer such that it cannot be properly programmed or read. The problem increases as the via is scaled to widths below 0.8 .mu.m.
What is needed is an anti-fuse structure that retains the simplicity of the planar A-Si approach as illustrated in FIG. 1, but which does not have the problems associated with this approach, especially as the via width is scaled below 0.8 m.